Low-voltage MOS linear transconductor/squarer and four-quadrant multiplier for analog VLSI

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 52, Issue 9, 2005, Pages 1721-1731

  Demosthenous, Andreas ^a   Panovic, Mladen ^a  

^a UNIVERSITY COLLEGE LONDON   (United Kingdom)

Author keywords

Analog signal processing; Flipped voltage follower; Four quadrant multiplier; Harmonic distortion; Linear transconductor; MOS analog circuits; Squarer

Indexed keywords

COMPUTATIONAL METHODS; ELECTRIC CONVERTERS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; FREQUENCY MULTIPLYING CIRCUITS; HARMONIC DISTORTION; SIGNAL PROCESSING; TRANSCONDUCTANCE; VLSI CIRCUITS;

ANALOG CIRCUITS; ANALOG SIGNAL PROCESSING; FLIPPED VOLTAGE FOLLOWER; FOUR-QUADRANT MULTIPLIER; LINEAR TRANSCONDUCTOR;

MOS DEVICES;

EID: 27144538972     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.852483     Document Type: Article

References (27)

1. M. Ismail and T. Feiz, Eds., Analog VLSI: Signal and Information Processing: McGraw-Hill, 1994.
2. E. K. F. Lee and P. G. Gulak, "Field programmable analog array based on MOSFET transconductance," Electron. Lett., vol. 28, pp. 28-29, Jan. 1992.
3. F. J. Kub, K. K. Moon, I. A. Mack, and F. M. Long, "Programmable analog vector-matrix multipliers," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 207-214, Feb. 1990.
4. W.-C. Fang, B. J. Sheu, O. T.-C. Chen, and J. Choi, "A VLSI neural processor for image data compression using self-organization networks," IEEE Trans. Neural Netw., vol. 3, no. 3, pp. 506-518, May 1992.
5. A. Tomasini, M. Brattoli, E. Chioffi, G. Colli, D. Gerna, and M. Pasotti, "B/W adaptive image grabber with analog motion vector estimator at 0.3 GOPS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1996, pp. 94-95.
6. G. Cauwenberghs and V. Pedroni, "A low-power CMOS analog vector quantizer," IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1278-1283, Aug. 1997.
7. G. T. Tuttle, S. Fallahi, and A. A. Abidi, "An 8b CMOS vector A/D converter," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1993, pp. 38-39.
8. D. Montanari, V. Houdt, G. Greseneken, and H. E. Maes, "Novel level-identifying circuit for flash multilevel memories," IEEE J. Solid-State Circuits, vol. 33, no. 6, pp. 1090-1095, June 1998.
9. C. Toumazou, D. Haigh, and J. Lidgey, Eds., The Current-Mode Approach. London, U.K.: The Institution of Electrical Engineers (IEE), 1990.
10. G. Han and E. Sanchez-Sinencio, "CMOS transconductance multipliers: a tutorial," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 12, pp. 1550-1563, Dec. 1998.
11. A. Nedungadi and T. R. Viswanathan, "Design of linear CMOS transconductance elements," IEEE Trans. Circuits Syst., vol. 31, no. 10, pp. 891-894, Oct. 1984.
12. T. L. Viswanathan, "CMOS transconductance element," Proc. IEEE, vol. 74, pp. 222-224, 1986.
13. M. F. Li, X. Chen, and Y. C. Lim, "Linearity improvement of CMOS transconductors for low supply applications," Electron. Lett., vol. 29, no. 12, pp. 1106-1107, Jun. 1993.
14. E. Seevink and R. F. Wassenaar, "A versatile CMOS linear tranconductor/square-law function circuit," IEEE J. Solid-State Circuits, vol. SC-22, no. 3, pp. 366-377, Jun. 1987.
15. J. Ramirez-Anguio, R. G. Carvajal, A. Torralba, J. Galan, A. P. Vega-Leal, and J. Tombs, "The flipped voltage follower: a useful cell for low-voltage low-power circuit design," in Proc. 2002 IEEE Int, Symp. Circuits Syst., Phoenix, AZ, May 2002, pp. 615-618.
16. M. Panovic and A. Demosthenous, "Analogue implementation of mean square error function for use in motion estimation" in Proc. PREP 2003, Exeter, U.K., Apr. 2003, pp. 163-164.
17. A. P. Nedungadi and R. L. Geiger, "High-frequency voltage-controlled continuous-time filter using linearized CMOS integrators," Electron. Lett., vol. 22, pp. 729-731, Jun. 1986.
18. H.-J. Song and C.-K. Kim, "A MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers," IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 841-848, Jun. 1990.
19. R. Castello and P. R. Gray, "A high-performance micropower switched-capacitor filter," IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp. 1122-1132, Dec. 1985.
20. V. Peluso, P Vancorenland, M. Steyaert, and W. Sansen, "900-mV differential class AB OTA for switched opamp applications," in Electron. Lett., Aug. 1997, vol. 33, pp. 1455-1456.
21. P.R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed. New York: Wiley, 2001.
22. B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2000.
23. austriamicrosystems AG, 0.8-μm CMOS Process Parameters, April 1997.
24. K. Kimura, "Analysis of an MOS four-quadrant analog multiplier using two-input squaring circuits with source followers," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 41, no. 1, pp. 72-75, Jan. 1994.
25. S.L. Garverick and C. G. Sodini, "Large-signal linearity of scaled MOS transistors," IEEE J. Solid-State Circuits, vol. SC-22, no. 2, pp. 282-286, Apr. 1987.
26. A.L. Coban, P. E. Allen, and X. Shi, "Low-voltage IC design in CMOS technology," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 42, pp. 995-958, Nov. 1995.
27. J. Ramirez-Angulo, S. Thoutam, A. López-Martin, and R. G. Carvajal, "Low-voltage CMOS analogue four quadrant multiplier based on flipped voltage followers," Electron. Lett., vol. 39, pp. 1771-1772, Dec. 2003.