Timed I/O test sequences for discrete event model verification

Lecture Notes in Artificial Intelligence (Subseries of Lecture Notes in Computer Science)

Volumn 3397, Issue , 2005, Pages 275-284

  Hong, Ki Jung ^a   Kim, Tag Gon ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING; COMPUTER SIMULATION; GRAPH THEORY; SPECIFICATIONS;

DISCRETE EVENT MODEL VERIFICATION; MODEL SPECIFICATIONS; SIMULATION MODEL; TIMED I/O TEST SEQUENCES;

MATHEMATICAL MODELS;

EID: 26844477982     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/978-3-540-30583-5_30     Document Type: Conference Paper

References (7)

1. J. Banks, D. Gerstein, and S. P. Searles, "Modeling process, validation, and verification of complex simulations: A survey", S.C.S Methodology and Validation, simulation series, Vol. 19, No. 1, pp 13-18, 1988.
2. Concepcion, and B. P. Zeigler, "DEVS formalism: a framework for hierarchical model development," IEEE Trans. Software Eng., vol. 14, no. 2, pp. 228-241, Feb. 1988.
3. W. Y. L. Chan, C. T. Vuong, M. R. Otp, "An improved protocol test generation procedure based on UIOS," ACM SIGCOMM Comp. Commun. Review,Symposium proc. communi. arch. & protocols , vol. 19, pp. 283-294, Aug. 1989.
4. A. T. Dahbura, K. K. Sabnani, and M. Ümit Uyar, "Formal nethods for generating protocol conformance test sequences," Proc. of the IEEE, vol. 78, pp. 1317-1325, Aug. 1990.
5. D. Lee, and M. Yannakakis, "Principles and methods of testing finite state machines-A survey," Proc of the IEEE, vol. 84, pp. 1090-1123, Aug. 1996.
6. A. En-Nouaary, R. Dssouli, and F. Khendek, "Timed Wp-method: Testing real-time systems," IEEE Trans. Software Eng., vol. 28, pp. 1023-1038, Nov. 2002.
7. K. J. Hong, and T. G. Kim, "A Verification Of Time Constrained Simulation Model Using Test Selection: A New Approach", In preparation, 2004.