A HyperTransport chip-to-chip interconnect tunnel developed using SystemC

Proceedings of the International Workshop on Rapid System Prototyping

Volumn , Issue , 2005, Pages 264-266

  Castonguay, Ami ^a   Savaria, Yvon ^a  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CELL TECHNOLOGY; HYPERTRANSPORT (HT) TUNNEL; PERFORMANCE SYSTEM; RAPID SYSTEM PROTOTYPING;

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; RAPID PROTOTYPING; TELECOMMUNICATION LINKS;

MICROPROCESSOR CHIPS;

EID: 26444607452     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RSP.2005.6     Document Type: Conference Paper

References (5)

1. HyperTransport Technology Consortium, Hypertransport I/O Link Specification Revision 2.00, Doc: HTC20031125-0035-0006, Aug. 2004.
2. The Open SystemC Initiative (OSCI), "SystemC v2.0.1 functional specification", Apr. 2002
3. Syed Rafay Hasan, Alexandre Landry, Yvon Savaria and Mohamed Nekili, "Design constraints of a HyperTransport-compatible network-on-chip", IEEE-NEWCAS'2004, Jun. 2004
4. C. Sauer, M. Gries, J.I. Gomez, K. Keutzer, "Towards a flexible network processor interface for RapidIO, Hypertransport, and PCI-Express", NP3 - HPCA10, Feb. 2004.
5. Djones Lettnin, Axel Braun, Martin Bodgan, Joachim Gerlach, Wolfgang Rosenstiel, "Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks", DATE'04, Feb. 2004