Design procedure for two-stage CMOS opamp with flexible noise-power balancing scheme

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 52, Issue 8, 2005, Pages 1508-1514

  Mahattanakul, Jirayuth ^a   Chutichatuporn, Jamorn ^b  

^a MAHANAKORN UNIVERSITY OF TECHNOLOGY   (Thailand)

^b RGY Hydraulic Company   (Thailand)

Author keywords

CMOS analog integrated circuits; Frequency compensation; Operational amplifier; Poles and zeroes

Indexed keywords

APPROXIMATION THEORY; CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; EQUIVALENT CIRCUITS; MOSFET DEVICES; OPTIMIZATION; POLES AND ZEROS; POLYNOMIALS; THERMAL NOISE; TRANSFER FUNCTIONS;

CMOS ANALOG INTEGRATED CIRCUITS; FREQUENCY COMPENSATION; NOISE POWER BALANCING;

OPERATIONAL AMPLIFIERS;

EID: 26444484319     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.851395     Document Type: Article

References (6)

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