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Volumn 26, Issue 9, 2005, Pages 619-621

High-performance/inductors on plastic substrate

Author keywords

CMOS integration; FR 4; Plastic substrate; RF inductor; Wafer transfer technology (WTT)

Indexed keywords

CMOS INTEGRATED CIRCUITS; MATHEMATICAL MODELS; SEMICONDUCTING POLYMERS; SILICON WAFERS; SUBSTRATES;

EID: 26444459805     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.854379     Document Type: Article
Times cited : (21)

References (11)
  • 1
    • 0033360139 scopus 로고    scopus 로고
    • "A study on substrate effects of silicon-based RF passive components"
    • C. P. Yue and S. S. Wong, "A study on substrate effects of silicon-based RF passive components," in IEEE MIT-S Dig., 1999, pp. 1625-1628.
    • (1999) IEEE MIT-S Dig. , pp. 1625-1628
    • Yue, C.P.1    Wong, S.S.2
  • 2
    • 2442669253 scopus 로고    scopus 로고
    • "Wafer-level packaging technology for high-Q on-chip inductors and transmission lines"
    • Apr
    • G. J. Carchon, W. D. Raedt, and E. Beyne, "Wafer-level packaging technology for high-Q on-chip inductors and transmission lines," IEEE Trans. Microw. Theory Tech., vol. 52, no. 4, pp. 1244-1251, Apr. 2004.
    • (2004) IEEE Trans. Microw. Theory Tech. , vol.52 , Issue.4 , pp. 1244-1251
    • Carchon, G.J.1    Raedt, W.D.2    Beyne, E.3
  • 3
    • 4444225321 scopus 로고    scopus 로고
    • "On-chip high-Q Cu inductors embedded in wafer-level chipscale package for silicon RF application"
    • K. Itoi, M. Sato, H. Abe, H. Sugawara, H. Ito, K. Okada, K. Masu, and T. Ito, "On-chip high-Q Cu inductors embedded in wafer-level chipscale package for silicon RF application," in IEEE MTF-S Dig., 2004, pp. 197-200.
    • (2004) IEEE MTF-S Dig. , pp. 197-200
    • Itoi, K.1    Sato, M.2    Abe, H.3    Sugawara, H.4    Ito, H.5    Okada, K.6    Masu, K.7    Ito, T.8
  • 5
    • 13444292413 scopus 로고    scopus 로고
    • "High-performance inductors integrated on porous silicon"
    • Feb
    • K. Chong, Y. Xie, K. Yu, D. Huang, and M. F. Chang, "High-performance inductors integrated on porous silicon," IEEE Electron Device Lett., vol. 26, no. 2, pp. 93-95, Feb. 2005.
    • (2005) IEEE Electron Device Lett. , vol.26 , Issue.2 , pp. 93-95
    • Chong, K.1    Xie, Y.2    Yu, K.3    Huang, D.4    Chang, M.F.5
  • 9
    • 21644485278 scopus 로고    scopus 로고
    • "New low-cost thermally stable process to reduce silicon substrate losses: A way to extreme frequencies for high volume Si technologies"
    • C. Detecheverry, W. D. Van Noort, and R. J. Havens, "New low-cost thermally stable process to reduce silicon substrate losses: A way to extreme frequencies for high volume Si technologies," in IEDM Tech. Dig., 2004, pp. 463-466.
    • (2004) IEDM Tech. Dig. , pp. 463-466
    • Detecheverry, C.1    Van Noort, W.D.2    Havens, R.J.3
  • 10


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.