0.25 μ m gate length N-InGaP/InGaAs/GaAs HEMT DCFL circuit with lower power dissipation than high-speed Si CMOS circuits

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 323-326

  Kuroda, S ^a   Suehiro, H ^a   Miyata, T ^a   Asai, S ^a   Hanyu, I ^a   Shima, M ^a   Hara, N ^a   Takikawa, M ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC LOSSES; GALLIUM COMPOUNDS; LOW POWER ELECTRONICS; TIMING CIRCUITS; VLSI CIRCUITS;

GATE LENGTH; HIGH SPEED; LOW-POWER DISSIPATION; NOISE MARGINS; SHORT-CHANNEL EFFECT; SI CMOS; SUPPLY VOLTAGES; VLSI FABRICATION;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 26344479847     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307370     Document Type: Conference Paper

References (12)

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