Concurrent symbol processing capable VLSI architecture for bit plane coder of JPEG2000

IEICE Transactions on Information and Systems

Volumn E88-D, Issue 8, 2005, Pages 1878-1884

  Gupta, Amit Kumar ^a   Nooshabadi, Saeid ^a   Taubman, David ^a,b  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

^b UNSW Australia   (Australia)

Author keywords

Bit plane coder; Concurrent symbol processing; JPEG2000; VLSI architecture

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER HARDWARE; CONSUMER PRODUCTS; COST EFFECTIVENESS; IMAGE COMPRESSION; STANDARDS;

BIT PLANE CODER; CONCURRENT SYMBOL PROCESSING; JPEG2000; VLSI ARCHITECTURE;

VLSI CIRCUITS;

EID: 26044480919     PISSN: 09168532     EISSN: 17451361     Source Type: Journal    
DOI: 10.1093/ietisy/e88-d.8.1878     Document Type: Article

References (8)

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