A 322MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Iida, M ^a   Kuroda, N ^a   Otsuka, H ^a   Hirose, M ^a   Yamasaki, Y ^a   Ohta, K ^a   Shimakawa, K ^a   Nakabayashi, T ^a   Yamauchi, H ^a   Sano, T ^b   Gyohten, T ^b   Maruta, M ^b   Yamazaki, A ^b   Morishita, F ^b   Dosaka, K ^b   Takeuchi, M ^b   Arimoto, K ^b  

^a Matsushita   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 25844507603     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Y. Taito et al., "A High Density Memory for SoC with a 143MHz SRAM Interface Using Sense-Synchronized-Read/Write," ISSCC Dig. Tech. Papers, pp. 306-307, Feb., 2003.
2. H. Pilo et.al., "A 5.6ns Random Cycle 144Mb DRAM with 1.4Gb/s/pin and DDR3-SRAM Interface," ISSCC Dig. Tech. Papers, pp. 308-309, Feb., 2003.
3. M. Aoki et al., "A 60ns 16Mbit CMOS DRAM with a Transposed Data-Line Structure," IEEE J. Solid-State Circuits, vol.23, no. 5, pp. 1113-1119, Oct., 1988.
4. F. Morishita et al., "A 312MHz 16Mb Random-Cycle Embedded DRAM Macro with 73μW Power-Down Mode for Mobile Applications," ISSCC Dig. Tech. Papers, pp. 202-203, Feb., 2004.