The design and implementation of a first-generation CELL processor - A multi-core SoC

2005 International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2005, Pages 49-52

  Pham, D ^a   Asano, S ^c   Bolliger, M ^a   Day, M N ^a   Hofstee, H P ^a   Johns, C ^a   Kahle, J ^a   Kameyama, A ^c   Keaty, J ^a   Masubuchi, Y ^c   Riley, M ^a   Shippy, D ^a   Stasiak, D ^a   Suzuoki, M ^b   Wang, M ^a   Warnock, J ^a   Weitzel, S ^a   Wendel, D ^a   Yamazaki, T ^b   Yazawa, K ^b  

^a IBM   (United States)

^b Sony Computer Entertainment Inc   (United States)

^c Toshiba America Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 25844507151     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2005.1502588     Document Type: Conference Paper

References (2)

1. B. Flachs et al, "The Microarchitecture of the Streaming Processor for a CELL Processor", Paper #7.4
2. T. Asano et al, "A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL Processor", Paper #26.7