A 400MHz random-cycle dual-port interleaved DRAM with striped-trench capacitor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Shirahama, M ^a   Agata, Y ^a   Kawasaki, T ^a   Nishihara, R ^a   Abe, W ^a   Kuroda, N ^a   Sadakata, H ^a   Uchikoba, T ^a   Takahashi, K ^a   Egashira, K ^a   Honda, S ^a   Miura, M ^a   Hashimoto, S ^a   Kikukawa, H ^a   Yamauchi, H ^a  

^a Matsushita   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; DECODING; SENSORS; SIGNAL PROCESSING; SPURIOUS SIGNAL NOISE;

CAPACITOR CELL; DUAL-PORT; WRITEBUS CIRCUIT;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 25844491228     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. http://www.mosys.com/news/whitepapers.html
2. J. Earth et al., "A 300 MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write," in ISSCC Dig. Tech. Papers, pp.392-393, Feb., 2002.
3. 2RAM)," IEEE J. Solid-State Circuits, vol.35, pp.1668-1672, Nov., 2000.
4. H. Pilo et al., "A 5.6-ns Random Cycle 144-Mb DRAM With 1.4 Gb/s/pin and DDR3-SRAM Interface," IEEE J. Solid-State Circuits, vol.38, pp.1974-1980, Nov., 2003.