A 125MHz burst-mode flexible read-while-write 256Mbit 2b/c 1.8V NOR flash memory

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Villa, C ^a   Vimercati, D ^a   Schippers, S ^a   Confalonieri, E ^a   Sforzin, M ^a   Polizzi, S ^a   La Placa, M ^a   Lisi, C ^a   Magnavacca, A ^a   Bolandrina, E ^a   Martinelli, A ^a   Dima, V ^a   Scavuzzo, A ^a   Calandrino, B ^a   Del Gatto, N ^a   Scardaci, M ^a   Mastroianni, F ^a   Pisasale, M ^a   Geraci, A ^a   Gaibotti, M ^a   Sali, M ^a   more..

^a STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 25844481726     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. M. Bauer et al., "A Multilevel-cell, 32Mb Flash Memory," ISSCC Dig. Tech. Papers, pp. 132-135, Feb., 1995.
2. 2 3V only 50MHz 64Mb 2b/cell CHE NOR Flash Memory," IEEE J. Solid-State Circuits, vol. 35, pp. 1655-1666, Nov., 2000.
3. B. Pathak, et al., "A 1.8V 100MHz Flexible Read While Write Flash Memory," ISSCC Dig. Tech. Papers, pp. 32-33, Feb., 2001.
4. H. A.Castro et al., "A 125MHz Burst Mode 0.18um 128Mbit 2 Bits per Cell Flash Memory," Symp. VLSI Technology, July, 2002.
5. , D. Helmhurst et al., "A 1.8V 128Mb 125MHz Multi-Level Cell Flash Memory with Flexible Read While Write," ISSCC Dig. Tech. Papers, pp. 286-287, Feb., 2003.