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Volumn 44, Issue 4, 2005, Pages 373-399

Unrestricted vs restricted cut in a tableau method for Boolean circuits

Author keywords

Boolean circuits; Cut rule; DPLL; Proof complexity; Satisfiability

Indexed keywords


EID: 25444528684     PISSN: 10122443     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10472-005-7034-1     Document Type: Article
Times cited : (34)

References (32)
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.