Scaling constraints in nanoelectronic random-access memories

Nanotechnology

Volumn 16, Issue 10, 2005, Pages 2251-2260

  Amsinck, Christian J ^a   Di Spigna, Neil H ^a   Nackashi, David P ^a   Franzon, Paul D ^a  

^a NORTH CAROLINA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; MATHEMATICAL MODELS; NANOTECHNOLOGY; TUNNEL JUNCTIONS;

INTERCONNECT ARCHITECTURES; MAGNETIC TUNNEL JUNCTIONS (MTJ); MOLECULAR DEVICES; SCALING CONSTRAINTS;

RANDOM ACCESS STORAGE;

EID: 25444522231     PISSN: 09574484     EISSN: None     Source Type: Journal    
DOI: 10.1088/0957-4484/16/10/047     Document Type: Article

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