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Volumn 1, Issue , 1999, Pages 383-386

Efficient multiplier architecture using optimized irreducible polynomial over GF((3n)3)

Author keywords

[No Author keywords available]

Indexed keywords

CANONICAL BASIS; COMPOSITE FIELDS; FINITE FIELDS; IRREDUCIBLE POLYNOMIALS; KARATSUBA-OFMAN ALGORITHM; MULTIPLICATION ALGORITHMS; MULTIPLIER ARCHITECTURE; VLSI IMPLEMENTATION;

EID: 2542543218     PISSN: 21593442     EISSN: 21593450     Source Type: Conference Proceeding    
DOI: 10.1109/TENCON.1999.818431     Document Type: Conference Paper
Times cited : (3)

References (9)
  • 1
    • 23144466105 scopus 로고
    • Multiple-Valued logic and special Purpose Processors : Overview and Future
    • May
    • M. Kameyama and T. Higuchi, "Multiple-Valued logic and special Purpose Processors : Overview and Future", The 12th Int'l Symp. M. V. L pp. 289-292, May 1982
    • (1982) The 12th Int'l Symp. M. V. L , pp. 289-292
    • Kameyama, M.1    Higuchi, T.2
  • 2
    • 0023994420 scopus 로고
    • Multiple-valued logic : A tutorial and application
    • April.
    • K. C. Smith, "Multiple-Valued Logic : A Tutorial and Application", Com. Mag, pp. 17-27, April. 1988
    • (1988) Com. Mag , pp. 17-27
    • Smith, K.C.1
  • 3
    • 0000362440 scopus 로고
    • Division and Bit-serial Multiplication over GF (m)
    • May
    • M. A. Hasan, V. K. Bhargava, "Division and Bit-serial Multiplication over GF (m)" IEE Proceeding-E, Vol. 139, No. 3, May 1992
    • (1992) IEE Proceeding-E , vol.139 , Issue.3
    • Hasan, M.A.1    Bhargava, V.K.2
  • 4
    • 0016105280 scopus 로고
    • Irreducible polynomials over composite galois fields and their appplications in coding techniques
    • Sept.
    • D. H. Green and I. S. Taylor, "Irreducible Polynomials over Composite Galois Fields and Their Appplications in Coding Techniques, " Proc. IEE, vol. 121, no., pp. 935-39, Sept. 1974
    • (1974) Proc. IEE , vol.121 , pp. 935-939
    • Green, D.H.1    Taylor, I.S.2
  • 5
    • 33746026926 scopus 로고
    • VLSI design for multiplication over finite fields GF ( 2m)
    • Berlin: Springer-verlag, mar.
    • E. D. Mastrovito, "VLSI Design for Multiplication over Finite Fields GF ( 2m), "Lecture Notes in Computer Science 357, pp. 297-309 Berlin: Springer-verlag, mar. l989
    • (1989) Lecture Notes in Computer Science , vol.357 , pp. 297-309
    • Mastrovito, E.D.1
  • 8
    • 0031998554 scopus 로고    scopus 로고
    • Efficient multiplier architectures for galois fields GF (24n)
    • Feb
    • C. Paar, Efficient Multiplier Architectures For Galois Fields GF (24n), IEEE Trans. Computer, vol. 47, No. 2, Feb 1998
    • (1998) IEEE Trans. Computer , vol.47 , Issue.2
    • Paar, C.1
  • 9
    • 85044443402 scopus 로고    scopus 로고
    • A study on irreducible polynomial for construction of parallel multiplier over GF (q")
    • J. Y Oo, H. S. Kim, A study on Irreducible Polynomial for construction of Parallel Multiplier Over GF (q"), Proceedings of IEEK Summer Conference '99, Vol. 22, No. 1, pp741-744
    • Proceedings of IEEK Summer Conference '99 , vol.22 , Issue.1 , pp. 741-744
    • Oo, J.Y.1    Kim, H.S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.