Simulation studies and experimental verification of the performance of a lithocell combination bake-chill station

Journal of Microlithography, Microfabrication and Microsystems

Volumn 3, Issue 2, 2004, Pages 332-338

  Narasimhan, Arunn ^a,b   Ramanan, Natarajan ^a,c  

^a Microlithography Division   (United States)

^b INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

^c Applied Thermal Technologies   (United States)

Author keywords

300 mm resist processing; Bake plate; Chemically amplified resist; Chill plate; Combination bake chill; Numerical simulation; Proximity bake; Thermal analysis; Throughput

Indexed keywords

300-NM RESIST PROCESSING; BAKE PLATE; CHEMICALLY AMPLIFIED RESIST; CHILL PLATE; COMBINATION BAKE CHILL; PROXIMITY BAKE;

ALUMINUM; COMPUTER SIMULATION; COMPUTER SOFTWARE; GEOMETRY; MATHEMATICAL MODELS; PHOTOLITHOGRAPHY; PHOTORESISTS; PRODUCTIVITY; SCANNING; SEMICONDUCTOR MATERIALS; TEMPERATURE CONTROL; THERMOANALYSIS; THROUGHPUT; WSI CIRCUITS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 2542504784     PISSN: 15371646     EISSN: None     Source Type: Journal    
DOI: 10.1117/1.1668269     Document Type: Article

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