A hybrid energy-estimation technique for extensible processors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 5, 2004, Pages 652-664

  Fei, Yunsi ^a   Ravi, Srivaths ^b   Raghunathan, Anand ^b   Jha, Niraj K ^a  

^a Princeton University   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

Application specific instruction set processor (ASIPs); Energy estimation; Extensible processor; Macromodel

Indexed keywords

BENCHMARKING; BUFFER STORAGE; EMBEDDED SYSTEMS; ENERGY UTILIZATION; INTELLECTUAL PROPERTY; REGRESSION ANALYSIS; SYSTEMS ANALYSIS;

APPLICATION-SPECIFIC INSTRUCTION SET PROCESSORS (ASIP); ENERGY ESTIMATION; EXTENSIBLE PROCESSORS; MACROMODEL;

PROGRAM PROCESSORS;

EID: 2542479965     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.826546     Document Type: Article

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