Universal masking on logic gate level

Electronics Letters

Volumn 40, Issue 9, 2004, Pages 526-528

  Golic J Dj ^a   Menicocci, R ^b  

^a TELECOM ITALIA   (Italy)

^b SAPIENZA UNIVERSITY OF ROME   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; CASCADE CONNECTIONS; CRYPTOGRAPHY; DIGITAL INTEGRATED CIRCUITS; LOGIC CIRCUITS; MICROELECTRONIC PROCESSING; TABLE LOOKUP;

BINARY WORDS; DIFFERENTIAL POWER ANALYSIS; MASKING BITS; RANDOM MASKING;

LOGIC GATES;

EID: 2542422064     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20040385     Document Type: Article

References (4)

1. Kocher, P., Jaffe, J., and Jun, B.: 'Differential power analysis', Advances in Cryptology-CRYPTO'99, Led. Notes Comput. Sci., 1999, Vol. 1666, pp. 388-397
2. Messerges, T., Dabbish, E., and Puhl, L.: 'Method and apparatus for preventing information leakage attacks on a microelectronic assembly', US Patent 6,295,606 B1 September 2001
3. Golic, J.Dj.: 'DeKaRT: a new paradigm for key-dependent reversible circuits', Cryptographic Hardware and Embedded Systems-CHES 2003, Lect. Notes Comput. Sci., 2003, Vol. 2779, pp. 98-112
4. Menicocci, R., and Pascal, J.: 'Elaborazione crittografica di dati digitali mascherati', Italian patent pending MI2003A001375, July 2003