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Volumn 40, Issue 9, 2005, Pages 1880-1887
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A 700+-mW class D design with dIrect battery hookup in a 90-nm process
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Author keywords
Class D amplifier; Common mode rejection ratio (CMRR); Efficiency; Electromagnetic interference (EMI); Low drop out regulator (LDO); Power supply rejection ratio (PSRR); Pulse width modulation (PWm); Signal to noise ratio (snr); System on chip (SOC)
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Indexed keywords
AMPLIFIERS (ELECTRONIC);
APPROXIMATION THEORY;
BANDWIDTH;
COST EFFECTIVENESS;
EFFICIENCY;
ELECTRIC POTENTIAL;
PULSE WIDTH MODULATION;
SIGNAL INTERFERENCE;
SIGNAL TO NOISE RATIO;
SWITCHING;
CLASS D AMPLIFIER;
COMMON MODE REJECTION RATIO (CMRR);
LOW DROP-OUT REGULATOR (LDO);
POWER SUPPLY REJECTION RATIO (PSRR);
SYSTEM-ON-CHIP (SOC);
CMOS INTEGRATED CIRCUITS;
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EID: 25144521662
PISSN: 00189200
EISSN: None
Source Type: Journal
DOI: 10.1109/JSSC.2005.848147 Document Type: Conference Paper |
Times cited : (75)
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References (12)
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