Modelling SystemC process behavior by the UML method state machines

Lecture Notes in Computer Science

Volumn 3475, Issue , 2005, Pages 112-121

  Riccobene, Elvinia ^a   Scandurra, Patrizia ^a  

^a UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SYSTEMS ANALYSIS;

SYSTEM ON CHIP (SOC); SYSTEMC LANGUAGE; SYSTEMC PROCESS STATE MACHINES; UML METHOD;

COMPUTER PROGRAMMING LANGUAGES;

EID: 24944581001     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11423331_11     Document Type: Conference Paper

References (9)

1. E. Riccobene, P. Scandurra, A. Rosti and S. Bocchio. A UML 2.0 Profile for SystemC. ST Microelectronics Technical Report, 2004.
2. G.Martin. UML and VCC. White paper, Cadence Design Systems, Inc, Dec. 1999.
3. G.Martin, L.Lavagno, J.L.Guerin. Embedded UML: a merger of real-time UML and co-design. In CODES, 2001.
4. OMG, The Model Driven Architecture (MDA). http://www.omg.org/mda/.
5. OMG, UML 2.0 OCL Final Adopted Specification, ptc/03-10-14.
6. The Open SystemC Initiative. SystemC. http://www.systemc.org.
7. Q.Zhu, R.Oishi, T.Hasegawa, T.Nakata. System-on-chip validation using UML and CWL. In Proc. of IEEE/ACM/IFIP CODES, 2004.
8. SysML Partners web site, http://www.sysml.org/.
9. OMG, UML 2.0 Superstructure Final Adopted Specification, ptc/03-08-02.