Design and implementation of a high-performance and silicon efficient arithmetic coding accelerator for the H.264 advanced video codec

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2005, Pages 411-416

  Nunez Yanez, José L ^a   Chouliaras, Vassilios A ^b  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

^b LOUGHBOROUGH UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE CODING; THROUGHPUT;

BINARY ARITHMETIC CODING (BAC); ENTROPY CODING; H.264 VIDEO COMPRESSORS; HARDWARE ARCHITECTURE;

ENCODING (SYMBOLS);

EID: 24944567533     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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2. G. Bjontegaard, "H.26L Test Model Long Term Number 4 (TML 4) draft0", ITU-TSG16/Q.6 Q15-J-72, June 2000.
3. S. M. Lei, "Efficient Multiplication-Free Arithmetic Codes", IEEE Transactions on Communications", Vol. 43, No. 12, pp. 2950-2958, 1995.
4. D. Marpe, H. Schwartz, T. Wiegand, "Context-Based Adaptive Arithmetic Coding in the H.264 Video Compression Standard", IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 7, pp. 620-636, 2003.
5. T. Stockhammer, D. Kontopodis, T. Wiegand, "Rate-distortion optimization for JVT/H.26L video coding inpacket loss environment", Proc. of 2002 Int.
6. K.K. Ong, et all "A High Throughput Context-Based Adaptive Arithmetic Coder for JPEG2000", IEEE International Symposium on Circuits and Systems, 2002.
7. M. Tarui et al, "High-Speed Implementation of JBIG Arithmetic Coder", Proceedings of the IEEE Region 10 Conference, 1999.
8. M. Ahmadvand, A. Shahrokhi, O. Fatemi, "A High-Speed Pipelined Architecture for the MQ-Coder of the JPEG2000 Standard", QSBC Symposium, March, 2004.