Generating efficient custom FPGA soft-cores for control-dominated applications

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2005, Pages 127-133

  L'Hours, Ludovic ^a  

^a UNIVERSITÉ DE RENNES 1   (France)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED FLOW; CODE SIZE; INSTRUCTION SETS; SOFT-CORES;

AUTOMATION; MATHEMATICAL MODELS; MICROCONTROLLERS; RESOURCE ALLOCATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 24944499033     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2005.37     Document Type: Conference Paper

References (14)

1. K. Atasu, L. Pozzi, and P. Ienne. Automatic Application-Specific Instruction-Set Extensions under Microarchitectural Constraints. In DAC '03: Proceedings of the 40th Conference on Design Automation, pages 256-261, New York, NY, USA, 2003. ACM Press.
2. M. Budiu, M. Sakr, K. Walker, and S. C. Goldstein. BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations. Lecture Notes in Computer Science, 1900:969-979, 2001.
3. A. Corporation. Stratix Device Handbook, chapter Stratix architecture. Altera, 2005.
4. X. Corporation. Virtex-II datasheet, chapter fonctionnai description. Xilinx, 2004.
5. C. W. Fraser, D. R. Hanson, and T. A. Proebsting. Engineering a Simple, Efficient Code-Generator Generator. ACM Letters on Programming Languages and Systems, 1:213-226, Sept. 1992.
6. J. Gray. Hands-on Computer Architecture - Teaching Processor and Integrated Systems Design with FPGAs. ISCA '00 Workshop on Comp. Arch. Education, 2000.
7. G. Hadjiyiannis, S. Hanono, and S. Devadas. ISDL: An Instruction Set Description Language for Retargetability. In Design Automation Conference, pages 299-302, 1997.
8. S. A. Ito, L. Carro, and R. P. Jacobi. System Design Based on Single Language and Single-Chip Java ASIP Microcontroller. In DATE, pages 703-709, 2000.
9. M. K. Jain, M. Balakrishnan, and A. Kumar. ASIP Design Methodologies : Survey and Issues. In Fourteenth International Conference on VLSI Design, pages 76-81, Jan. 2001.
10. D. Lavenier, S. Guyétant, S. Derrien, and S. Rubini. A Reconfigurable Parallel Disk System for Filtering Genomic Banks. ERSA'03, Engineering of Reconfigurable Systems and Algorithms, 2003.
11. S.S. Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers Inc., 1997.
12. A. Nohl, V. Greive, G. Braun, A. Andreas, R. Leupers, O. Schliebusch, and H. Meyr. Instruction Encoding Synthesis for Architecture Exploration using Hierarchical Processor Models. In Proceedings of the 40th conference on Design automation, pages 262-267. ACM Press, 2003.
13. S. Pees, A. Hoffmann, V. Zivojnovic, and H. Meyr. LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. In Design Automation Conference, pages 933-938, 1999.
14. P. Yu and T. Mitra. Scalable Custom Instructions Identification for Instruction-Set Extensible Processors. In CASES '04: Proceedings of the 2004 international Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pages 69-78, New York, NY, USA, 2004. ACM Press.