Testability beyond JTAG

EE: Evaluation Engineering

Volumn 44, Issue 9, 2005, Pages 48-54

  Ungar, Louis Y ^a,b  

^a ATE Solutions ^*  (United States)

^b ATE Solutions   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN-SELF-TEST (BIST); CIRCUIT BOARDS; IN-SYSTEM PROGRAMMING; JTAG;

ECONOMIC AND SOCIAL EFFECTS; FIELD PROGRAMMABLE GATE ARRAYS; PROBLEM SOLVING; PULSED LASER DEPOSITION; STANDARDIZATION; TESTING;

NETWORKS (CIRCUITS);

EID: 24944497610     PISSN: 01490370     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Review

References (4)

1. TP 101C - Surface-Mount Technology Association Testability Guidelines, SMTA 2002.
2. The Testability Director, Version 3.2, A.T.E. Solutions, 2005, http://www. besttest.com/OurProducts/Testability Director
3. Goodman, D., Jahangiri, J., Clark, C.J., and Ungar, L.Y., "Planning for Built-in Self Test (BIST) to Handle Your Testing Needs," The BestTest Newsletter, Dec. 1, 2004, http://www.besttest.com/BestTest_Newsletters/ Dec_1_2004.htm
4. Ungar, L.Y. and Ambler, T., "Economics of Built-in Self Test," IEEE Design & Test Magazine, September-October 2001, pp. 70-79.