An efficient hardware-based fault diagnosis scheme for AES: Performances and cost

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2004, Pages 130-138

  Bertoni, Guido ^a   Breveglieri, Luca ^b   Koren, Israel ^c   Maistri, Paolo ^b  

^a STMICROELECTRONICS   (Italy)

^b POLITECNICO DI MILANO   (Italy)

^c University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT DETECTION; HARDWARE FAULTS; LATENCY; SCHEDULE UNITS;

ERROR ANALYSIS; HARDWARE; RELIABILITY; SCHEDULING; STANDARDS;

FAULT TREE ANALYSIS;

EID: 24944450510     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2004.1347833     Document Type: Conference Paper

References (18)

1. M. Akkar, C. Giraud, "An Implementation of DES and AES, Secure against some Attacks," Proceedings of CHES'01, pp. 315-325, 2001.
2. Amphion, "High Performance AES (Rijndael) Encryption - Ultra Fast," Product Datasheet, http://www.amphion.com/capture.asp?doc=cs5240.
3. F. Bao, R. Deng, Y. Han, A. Jeng, D. Narasimhalu, T. Nagir, "Breaking Public Key Cryptosystems on Tamper Resistant Devices in the Presence of Transient Faults," The Second Workshop on Secure Protocols, (Pads), April, 1997, LNCS, Springer-Verlag, 1997.
4. G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, "Error Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard," IEEE Transactions on Computers, Special Issue on Cryptographic Hardware and Embedded Software, pp. 492-505, April 2003.
5. G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, "Detecting and locating faults in VLSI implementations of the Advanced Encryption Standard," Proc. of the 2003 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 105-113, 2003.
6. D. Boneh, R. DeMillo, R. Lipton, "On the Importance of Eliminating Errors in Cryptographic Computations," Journal of Cryptology, vol. 14, pp. 101-119, 2001.
7. P. Chodowiec, K. Gaj, "Very Compact FPGA Implementation of the AES Algorithm," Cryptographic Hardware and Embedded Systems - CHES 2003, Lecture Notes in Computer Science, vol. 2779, pp. 319-333, Springer-Verlag, 2003.
8. C. Giraud, "DFA on AES," http://eprint.iacr.org/2003/008.ps.gz
9. B. Gladman, "A Specification for Rijndael, the AES Algorithm," fp.gladman.plus.com/, 2001.
10. R. Karri, W. Kaijie, P. Mishra, K. Yongkook, "Fault-based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture," Proc. of the 2001 Defect and Fault Tolerance in VLSI Systems, pp. 418-426, 2001.
11. R. Karri, G. Kuznetsov, M. Goessel, "Parity-based concurrent error detection in symmetric block ciphers," Proceedings of International Test Conference 2003 - ITC 2003, Volume 1, ISSN 1089-3539, pp. 919-926, 2003.
12. R. Karri, G. Kuznetsov, M. Goessel, "Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers," Cryptographic Hardware and Embedded Systems - CHES 2003, Lecture Notes in Computer Science, vol. 2779, pp. 319-333, Springer-Verlag, 2003.
13. R. Lidl, H. Niederreiter, Introduction to Finite Fields and their Applications, Cambridge University Press, 1986.
14. S. Morioka, A. Satoh, "A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture." Proceedings of 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 98-103, 2002.
15. National Institute of Standards and Technologies, "Announcing the Advanced Encryption Standard (AES)," Federal Information Processing Standards Publication, n. 197, November 26, 2001.
16. A. Satoh, S. Morioka, K. Takano, S. Munetoh, "A Compact Rijndael Hardware Architecture with S-Box Optimization," Advances in Cryptology - ASIACRYPT 2001, Lecture Notes in Computer Science, vol. 2248, Springer-Verlag, pp. 239-254, 2001.
17. F.-X. Standaert, G. Rouvroy, J.-J. Quisquater, J.-D. Legat, "Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs," Cryptographic Hardware and Embedded Systems - CHES 2003, Lecture Notes in Computer Science, vol. 2779, Springer-Verlag, pp. 334-350, 2003.
18. I. Verbauwhede, P. Schaumont, H. Kuo, "Design and performance testing of a 2.29-GB/s Rijndael processor," IEEE Journal of Solid-State Circuits, Vol. 38, Issue 3, pp. 569-572, 2003.