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Volumn 1, Issue , 2005, Pages 586-591

AES power attack based on induced cache miss and countermeasure

Author keywords

AES; Block Cipher; Cache; Cache Miss; Power Analysis

Indexed keywords

COMPUTER SIMULATION; COMPUTER SOFTWARE; CRYPTOGRAPHY;

EID: 24744459871     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/itcc.2005.62     Document Type: Conference Paper
Times cited : (95)

References (7)
  • 1
    • 0003510233 scopus 로고    scopus 로고
    • Evaluating future microprocessors: The simplescalar tool set
    • D. Burger, T. M. Austin, and S. Bennett. Evaluating future microprocessors: The simplescalar tool set. Technical Report CS-TR-1996-1308, 1996.
    • (1996) Technical Report , vol.CS-TR-1996-1308
    • Burger, D.1    Austin, T.M.2    Bennett, S.3
  • 3
    • 21044454999 scopus 로고    scopus 로고
    • Challenges for architectural level power modeling
    • R. Melhem and R.Graybill, editors
    • N. S. Kim, T. Austin, T. Mudge, and D. Grunwald. Challenges for architectural level power modeling. In R. Melhem and R.Graybill, editors, Power-Aware Computing. 2001.
    • (2001) Power-aware Computing
    • Kim, N.S.1    Austin, T.2    Mudge, T.3    Grunwald, D.4
  • 4
    • 1942457187 scopus 로고    scopus 로고
    • Theoretical use of cache memory as a cryptanalytic side-channel
    • Department of Computer Science, University of Bristol, June
    • D. Page. Theoretical use of cache memory as a cryptanalytic side-channel. Technical Report CSTR-02-003, Department of Computer Science, University of Bristol, June 2002.
    • (2002) Technical Report , vol.CSTR-02-003
    • Page, D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.