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Volumn 3449, Issue , 2005, Pages 215-224

A genetic algorithm for VLSI floorplanning using O-tree representation

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; MATHEMATICAL TRANSFORMATIONS; PROBLEM SOLVING; SEARCH ENGINES; TREES (MATHEMATICS); VLSI CIRCUITS;

EID: 24644516698     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/978-3-540-32003-6_22     Document Type: Conference Paper
Times cited : (24)

References (9)
  • 6
    • 0029699978 scopus 로고    scopus 로고
    • An immunity based genetic algorithm and its application to the VLSI floorplan design problem
    • Tazawa I., Koakutsu S., Hirata H.: An Immunity based Genetic Algorithm and Its Application to the VLSI Floorplan Design Problem. Proc. Int. Conf. on Evolutionary Computation. (1996) 417-421
    • (1996) Proc. Int. Conf. on Evolutionary Computation , pp. 417-421
    • Tazawa, I.1    Koakutsu, S.2    Hirata, H.3
  • 9
    • 0036670463 scopus 로고    scopus 로고
    • VLSI placement and area optimization using a genetic algorithm to bread normalized postfix expressions
    • Valenzuela C.L., Wang P.Y.: VLSI Placement and Area Optimization Using a Genetic Algorithm to Bread Normalized Postfix Expressions. IEEE Transactions on Evolutionary Computation. 6 (2002) 390-401
    • (2002) IEEE Transactions on Evolutionary Computation , vol.6 , pp. 390-401
    • Valenzuela, C.L.1    Wang, P.Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.