Checking timed büchi automata emptiness efficiently

Formal Methods in System Design

Volumn 26, Issue 3, 2005, Pages 267-292

  Tripakis, Stavros ^a   Yovine, Sergio ^a   Bouajjani, Ahmed ^b  

^a VERIMAG   (France)

^b UNIVERSITÉ PARIS DIDEROT   (France)

Author keywords

On the fly verification; Symbolic model checking; Timed automata; Verification tools

Indexed keywords

COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SIMULATION; FORMAL LOGIC; GRAPH THEORY; MATHEMATICAL MODELS; SYSTEMS ANALYSIS;

ON-THE FLY VERIFICATION; SYMBOLIC MODEL-CHECKING; TIMED AUTOMATA; VERIFICATION TOOLS;

AUTOMATA THEORY;

EID: 24644487788     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10703-005-1632-8     Document Type: Article

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