Sub-90 nanometer variability is here to stay...deal with it

Electronic Engineering Times

Volumn , Issue 1385, 2005, Pages 26-28

  Hurat, Philippe ^a   Wang, Yao Ting ^a   Verghese, Nishath K ^a  

^a Clear Shape Technologies   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

IC MANUFACTURING VARIATIONS; PROCESS PARAMETERS; RANDOM VARIATIONS; SEMICONDUCTOR INDUSTRY;

COMPUTER SIMULATION; COPPER; ELECTRIC CONDUCTIVITY; ELECTRON SCATTERING; GRAIN BOUNDARIES; INTEGRATED CIRCUIT MANUFACTURE; LITHOGRAPHY; OPTICAL INTERCONNECTS; PARAMETER ESTIMATION; SPURIOUS SIGNAL NOISE;

INTEGRATED CIRCUIT LAYOUT;

EID: 24644474659     PISSN: 01921541     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Review

References (4)

1. Advanced Reticle Symposium, June 28, 2005
2. "Benchmarks for Interconnect Parasilic Resistance and Capacitance" Proc. of ISQED 2003
3. NEC Statement, 11th June, 2003
4. EETimes, 18th July, 2005