Accurate Delay Models For Digital Bicmos

IEEE Transactions on Electron Devices

Volumn 39, Issue 6, 1992, Pages 1456-1464

  Cham, Kit M ^c  

^a HEWLETT PACKARD LABORATORIES   (United States)

^b STANFORD UNIVERSITY   (United States)

^c HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 2442757838     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.137326     Document Type: Article

References (12)

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2. A. Bellaouar, S. Embabi, and M. Elmasry, “Scaling of digital Bi-CMOS circuits,” IEEE J. Solid-State Circuits, vol. 25, no. 4, pp. 932–941, Aug. 1990.
3. H. J. De Los Santos and B. Hoefflinger, “Optimization and scaling of CMOS-bipolar drivers for VLSI interconnects,” IEEE Trans. Electron Devices, vol. ED-33, no. 11, 1722–1730, Nov. 1986.
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8. P. Raje, “Analysis, design and scaling of BiCMOS for digital logic,” Ph.D. dissertation, Stanford University, Stanford, CA, 1991.
9. I. Getreu, “Modeling the bipolar transistor,” Tech. Rep., Tektronix Inc., 1979.
10. P. A. Raje, K. C. Saraswat, and K. M. Cham, “A new methodology for design of BiCMOS gates and comparison with CMOS,” IEEE Trans. Electron Devices, vol. 39, no. 2, pp. 339–347, Feb. 1992.
11. T. Ikeda, A. Watanabe, Y. Nishio, I. Masuda, N. Tamba, M. Odaka, and K. Ogiue, “High-speed BiCMOS technology with a buried twin well structure,” IEEE Trans. Electron Devices, vol. ED-34, no. 6, pp. 1304–1310, June 1987.
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