A 0.13μm CMOS four-channel ADSL2+ analog front-end for CO applications with 75mW per channel

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Oswal, S ^a   Mujica, F ^b   Prasad, S ^a   Srinivasa, R ^a   Sharma, B ^a   Raychoudhary, A ^a   Khasnis, H ^a   Sharma, A ^a   Sriram, R ^a   Vijayvardhan, B ^a   Menon, R ^a   Gireesh, R ^a   Ahuja, N ^a   Gambhir, M ^a   Sadafale, M ^a  

^a TEXAS INSTRUMENTS   (India)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CORE; MODEM PERFORMANCE; NETWORK PROCESSORS; TIMING RECOVERY;

AMPLIFIERS (ELECTRONIC); DIGITAL FILTERS; HARMONIC ANALYSIS; INTEGRATION; MODEMS; OPTIMIZATION; POWER TRANSMISSION; SAMPLING; SENSITIVITY ANALYSIS; SIGNAL PROCESSING; TOPOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 2442705550     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. S. S. Lee, "Integration and System Design Trends of ADSL Analog Front Ends and Hybrid Line Interfaces," IEEE CICC Dig. Tech.Papers, May 2002.
2. H. Weinberger et al.,"An ADSL Full-Rate Analog Front End IC with Integrated Line Driver," IEEE J. Solid-State Circuits, vol. 37, pp 857-865, Jul. 2002.
3. J. P. Cornil et al.,"A 0.5μm CMOS ADSL Analog Front-End IC," ISSCC Dig. Tech. Papers, pp 238-39, Feb. 1999.