An 800MHz embedded DRAM with a concurrent refresh mode

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2003, Pages 160-161

  Kirihata, Toshiaki ^a   Parries, Paul ^a   Hanson, David ^a   Kim, Hoki ^a   Golz, John ^a   Fredeman, Gregory ^a   Rajeevakumar, Raj ^a   Griesemer, John ^a   Robson, Norman ^a   Cestero, Alberto ^a   Wordeman, Matt ^a   Iyer, Subramanian ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED DRAM; LOGIC TECHNOLOGY; MEMORY AVAILABILITY; MULTI BANKING OPERATIONS;

COMPUTER SIMULATION; ELECTRIC FREQUENCY CONTROL; EMBEDDED SYSTEMS; LOGIC CIRCUITS; LOGIC DEVICES; PARALLEL PROCESSING SYSTEMS; STORAGE ALLOCATION (COMPUTER);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 2442679209     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)