Si nanodevices for random number generating circuits for cryptographic security

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Fujita, S ^a   Uchida, K ^a   Yasuda, S ^a   Ohba, R ^a   Nozaki, H ^a   Tanamoto, T ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

A/D CONVERTER; CRYPTOGRAPHIC SECURITY; RNGC; TRAPPED ELECTRON;

ADCOCK DIRECTION FINDERS; AMPLIFIERS (ELECTRONIC); ELECTRIC NETWORK ANALYSIS; ELECTRIC SIGNAL SYSTEMS; LSI CIRCUITS; MOBILE COMPUTING; NANOSTRUCTURED MATERIALS; PERCOLATION (COMPUTER STORAGE); RANDOM NUMBER GENERATION; SHRINKAGE; SILICON COMPOUNDS; SMART CARDS;

CRYPTOGRAPHY;

EID: 2442660132     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. White paper prepared for Intel Corporation, 1999, http://www.intel.com/ design/security/rng/rng.html
2. Random Master™ (Tbshiba), USP: 6195669.
3. S. Yasuda et al., International Conference on Solid State Devices and Materials, pp. 250-251, 2002.
4. K. Uchida et al., IEEE International Electron Devices Meeting Technical Digest, pp. 47-50, 2002.