PowerPC 970 in 130nm and 90nm technologies

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2003, Pages

  Rohrer, Norman J ^a   Canada, Miles ^a   Cohen, Erwin ^a   Ringler, Mat ^a   Mayfield, Mike ^a   Sandon, Peter ^a   Kartschoke, Paul ^a   Heaslip, Jay ^a   Allen, James ^a   McCormick, Peter ^a   Pflüger, Thomas ^b   Zimmerman, Jeff ^a   Lichtenau, Cedric ^b   Werner, Tobias ^a   Salem, Gerard ^a   Ross, Mike ^a   Appenzeller, David ^a   Thygesen, Dana ^a  

^a IBM   (United States)

^b IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH BANDWIDTH PROCESSOR BUS; OPTIMUM PIPE STAGES; POLY FUSES; SEMI-CUSTOM DATAFLOW ASSEMBLY;

BANDWIDTH; BUFFER CIRCUITS; CACHE MEMORY; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DATA FLOW ANALYSIS; ELECTRIC INVERTERS; ELECTRIC NETWORK TOPOLOGY; INPUT OUTPUT PROGRAMS; OPTIMIZATION; PHASE LOCKED LOOPS; SILICON ON INSULATOR TECHNOLOGY;

MICROPROCESSOR CHIPS;

EID: 2442651667     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)