A 109.5mW 1.2V 600M texels/s 3-D graphics engine

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Imai, Masatoshi ^a   Nagasaki, Tanio ^a   Sakamoto, Junichi ^a   Takeuchi, Hideki ^a   Nagano, Hidetoshi ^a   Iwasaki, Seigo ^a   Hatakenaka, Mikako ^a   Fujita, Junichi ^a   Keino, Kenji ^b   Motomura, Tetsuo ^b   Ueda, Tohru ^b   Niki, Taichi ^b   Tomikawa, Hideaki ^b  

^a Sony Kihara Research Center

^b SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COORDINATE-BASED SET-ASSOCIATIVE CACHE SYSTEM (CBACS); FLOATING MULTIPLY-ACCUMULATE UNIT (FMAC); FLOATING-POINT GEOMETRY ENGINE (GE); RASTERIZATION ENGINE (RE);

DATA PROCESSING; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; HIGH DEFINITION TELEVISION; NATURAL FREQUENCIES; OPTICAL RESOLVING POWER; STORAGE ALLOCATION (COMPUTER); TRANSISTORS;

COMPUTER GRAPHICS;

EID: 2442651353     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Masatoshi Kameyama, et al., "3D Graphics LSI Core for Mobile Phone Z3D," Proceedings of Graphics Hardware 2003, pp.60-67, Jul 2003.
2. Chi-Weon Yoon, et al., "A 80/20MHz 160mW Multimedia Processor Integrated with Embedded DRAM, MPEG-4 Accelerator, and 3D Rendering Engine for Mobile Applications," ISSCC Dig. Tech. Papers, pp.142-143, Feb. 2001.
3. Ramchan Woo, et al., "A 120-mW 3-D Rendering Engine With 6-Mb Embedded DRAM and 3.2-GB/s Runtime Reconfigurable Bus for PDA Chip," IEEE J. Solid State Circuits, vol. 37, no. 10, Oct 2002.
4. Ramchan Woo, et al., "A 210mW Graphics LSI Implementing Full 3D Pipeline with 264Mtexels/s Texturing for Mobile Multimedia Applications," ISSCC Dig. Tech. Papers, pp.44-45, Feb 2003.