ASSESSMENT OF CHIP-SCALE PACKAGE DESIGN OPTIONS

ASME International Mechanical Engineering Congress and Exposition, Proceedings (IMECE)

Volumn 1997-AF, Issue , 1997, Pages 15-20

  Teng, Sue Y ^a   Guo, Yifan ^a   Sarihan, Vijay ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PROGRAMS; CHIP SCALE PACKAGES; ELASTICITY; FLIP CHIP DEVICES; STRUCTURAL DESIGN;

ASSEMBLY INFRASTRUCTURE; CHIP SIZE PACKAGE; CHIP-SCALE PACKAGE; DESIGN OPTION; FUNCTIONAL DENSITY; LOW-COSTS; PACKAGE DESIGNS; PACKAGE DEVELOPMENT; PORTABLE PRODUCTS; SPACE CONSUMPTION;

FINITE ELEMENT METHOD;

EID: 2442631595     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1115/IMECE1997-0811     Document Type: Conference Paper

References (8)

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3. Guo, Y. and Corbin, J. S., 1995, "Reliability of Ceramic Ball Grid Array Assembly", Ball Grid Array Technology. Chapter 8, Mc Graw-Hill, Inc.
4. Koehler, C, Tessier, T., et al., 1997, 'A User-Focused Chip Scale Packaging Solution", Proceedings from the 2nd International Conference on Chip Scale Packaging.
5. Matsuda, S., Kata, K., and Hagimoto, E., 1995, "Simple-Structure, Generally Applicable Chip-Scale Package", Proceedings 45th Electronic Components & Technology Conference.Vol 114, pp 218-223.
6. Sarihan, V., 1993 'Temperature Dependent Viscoplastic Simulation of Controlled Collapse Solder Joint under Thermal Cycling", ASME Transactions: Journal of Electronic Packaging, vol. 115, pp.16-21.
7. Sarihan, V., 1994, "Energy Based Methodology for Damage and Life Prediction of Solder Joints Under Thermal Cycling", IEEE Transactions on CPMT part B: Advanced Packaging.
8. Yasunaga, M., Baba, S., et al, 1995, "Chip Scale Package: 'A Lightly Dressed LSI Chip", TF.EE Trans. Compon. Packag. Manuf. Technol., Voi.18, no.3, pp 451-457.