A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 545-546

  Miyazaki, Takahito ^a   Hashimoto, Masanori ^a,b   Onodera, Hidetoshi ^a  

^a KYOTO UNIVERSITY   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

PHASE FREQUENCY DETECTORS (PFD); POWER CONSUMPTION; RING OSCILLATORS; VOLTAGE CONTROLLED OSCILLATORS (VCO);

CMOS INTEGRATED CIRCUITS; DIODES; ELECTRIC CLOCKS; ELECTRIC INDUCTORS; ELECTRIC INVERTERS; FABRICATION; JITTER; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS;

PHASE LOCKED LOOPS;

EID: 2442622349     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A. Hajimiri and T. H. Lee, "The Design of Low Noise Oscillators," Kluwer Academic Publishers, 1999.
2. "International Technology Roadmap for Semiconductors 1999," SIA, Semantech Inc., 1999.
3. K. Kundert, "Modeling Jitter in PLL-based Frequency Synthesizers," http://www.designers-guide.com
4. J. J. Rael and A. A. Abidi, "Physical Processes of Phase Noise in Differential LC Oscillators," Proc. CICC, pp. 569-572, 2000.
5. "Standard SPICE model based on ITRS'99," http://lowpower.iis.u- tokyo.ac.jp/~ina/index_e.html