Toward stochastic design for digital circuits - Statistical static timing analysis

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 762-767

  Tsukiyama, Shuji ^a  

^a CHUO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC POTENTIAL; PRINTED CIRCUIT DESIGN; PROBABILITY; STATISTICAL METHODS; VLSI CIRCUITS;

STATICAL TIMING ANALYSIS; STOCHASTIC DESIGN; SUB-MICRON TECHNOLOGY;

DIGITAL CIRCUITS;

EID: 2442527628     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (33)

1. K.Bernstein, K.M.Carrig, C.M.Durham, P.R.Hansen, D.Hogenmiller, E.J.Nowek, N.J.Rohrer, High Speed CMOS Design Styles, Kluwer Academic Pub., 1999.
2. S.R.Nassif, "Delay variability: Sources, impacts and trends," Dig. Tech. Papers ISSCC, pp.368-369, 2000.
3. N.Shigyo, "An investigation of response surfaces among process, device and circuit using analytical model," Proc. International Workshop on Statistical Metrology, 2000.
4. K.A.Bowman, S.G.Duvall, and J.D.Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," IEEE J. Solid-State Circuits, vol.37, no.2, pp.183-190, 2001.
5. M.Orshansky, L.Milor, P.Chen, K.Keutzer, and C.Hu, "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits," IEEE Trans. CAD/ICAS, vol.21, no.5, pp.544-553, 2002.
6. C. Visweswariah, "Death, taxes and failing chips," Proc. DA Conf., pp.343-347, 2003.
7. S.Borkar, T.Karnik, S.Narendra, J.Tshanz, A.Keshavarzi, V.De, "Parameter variations and impact on circuits and microarchitecture," Proc. DA Conf., pp.338-342, 2003.
8. K.Okada and H.Onodera, " Statistical modeling of device characteristics with systematic variability," pp.529-536, 2001.
9. M.Orshansky and K.Keutzer, "A general probabilistic framewaork for worst case timing analysis," Proc. DA Conf., pp.556-561, 2002.
10. M.A.Escalante and N.J.Dimopoulos, "A probabilstic timing analysis for synthesis in microporcessor interface design," Proc. IEEE Pasific Rm Conf. Comm., Computers and Signal Processing, pp.277-280, 1995.
11. X.L.Bai, C.Visweswariah, P.N.Strenski, D.J.Hathaway, "Uncertainty- aware circuit optimization," Proc. DA Conf., pp.58-63, 2002.
12. P.Gopalakrishnan, A.Odabasioglu, L.Pileggi, and S.Raje, "An analysis of the wire-load model uncertainty problem," IEEE Trans. CAD/ICAS, vol.21, no.1, pp.23-31, 2002.
13. I.A.Ferzli and F.N.Najm, "Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations," Proc. DA Conf., pp.856-859, 2003.
14. H.-F.Jyu, S.Malik, S.Devadas, and K.Keutzer, "Statistical timing analysis of combinatorial logic circuits," IEEE Trans. VLSI Systems, vol.1, no.2, pp.126-137, 1993.
15. R.B.Lin and M.C.Wu, "A new statistical approach to timing analysis of VLSI circuits," Proc. 11th Int. Conf. on VLSI Design, pp.507-513, 1997.
16. M.Berkelaar, "Statistical delay calculation, a linear time method," Proc. Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 15-24, 1997.
17. S.Tsukiyama, M.Tanaka, and M.Fukui, "An algorithm for statistical static timing analysis considering correlations between delays," IEICE Trans. Fundamentals, vol.E84-A, no. 11, pp.2746-2754, 2001. also in Proc. ASP-DAC, pp.353-358, 2001.
18. S.Tsukiyama, M.Tanaka, and M.Fukui, "An algorithm for statistical static timing analysis considering correlations between delays," IEICE Trans. Fundamentals, vol.E84-A, no. 11, pp.2746-2754, 2001. also in Proc. ASP-DAC, pp.353-358, 2001.
19. J.J.Liou, K.T.Cheng, S.Kundu, and A.Krstic, "Fast statistical timing analysis by probabilistic event propagation," Proc. DA Conf., pp.661-666, 2001.
20. J.J.Liou, A.Krstic, L.C.Wang, and K.T.Cheng, "False-path-aware statistical timing analysis and efficient path selection for delay tseting and timing validation," Proc. DA Conf., pp.566-569, 2002.
21. E.Ando, M.Yamashita, T.Nakata, Y.Matsunaga, "The statistical longest path problem and its application to delay analysis of logical circuits," Proc. DA Symp., pp.265-270, 2002 (In Japanese).
22. A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda, "Statistical delay computation considering spatial correlations," Proc. ASP-DAC, pp.271-276, 2003.
23. A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Statistical timing analysis using bounds," Proc. Design Automation and Test in Europe Conf. (DATE), pp.62-67, 2003.
24. A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Computation and refinement of statistical bounds on circuit delay," Proc. DA Conf., pp.348-353, 2003.
25. A.Krstic, L.C.Wang, K.T.Cheng, and J.J.Liou, "Diagnosis of delay defects using statistical timing models," Proc. IEEE VLSI Test Symp., pp.566-569, 2003.
26. J.A.G.Jess, K.Kalafala, S.R.Naidu, R.H.J.M.Otten, C.Visweswariah, "Statistical timing for parametric yield prediction of digital integrated circuits," Proc. DA Conf., pp.932-937, 2003.
27. H.Chen and D.Du, "Path sensitization in critical path problem," IEEE Trans. Computer-Aided Design of ICs and Systems, vol.12, no.2, pp. 196-207, 1993.
28. K.Nishida, K.Okada, M.Ohnishi, A.Yamada, T.Kambe, "Improving a high-level synthesis system using automatic false-path detection," Proc. the 13th Workshop on Circuits and Systems in Karuizawa, pp.237-262, 2000 (in Japanese).
29. P.Ashar, S.Dey, and S.Malik, "Exploiting multicycle false paths in the performance optimization of sequential logic circuits," IEEE Trans. Computer-Aided Design of ICs and Systems, vol. 14, no.9, pp. 1067-1075, 1995.
30. D.Yanagi and S.Tsukiyama, "Distribution of critical path delays in a combinatorial circuit," Proc. 2002 Int. Tech. Conf. on Circuits/ Systems, Computers and Communications, pp. 1300-1303, 2002.
31. M.Uehata, M.Tanaka, M.Fukui, S.Tsukiyama, "False paths elimination in statistical static timing analysis," ibid., pp.357-360, 2002.
32. M.Hashimoto and H.Onodera, "A performance optimization method by gate resizing based on statistical static timing analysis," IEICE Trans. Fundamentals, vol.83E-A, no. 12, pp.2558-2568, 2000.
33. E.T.A.F.Jacobs and M.R.C.M.Berkelaar, "Gate sizing using a statistical delay model," Proc. Design Automation and Test in Europe (DATE), pp.283-290, 2000.