A mulitple level network approach for clock skew minimization with process variations

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 263-268

  Mori, Makoto ^a   Chen, Hongyu ^a   Yao, Bo ^a   Cheng, Chung Kuan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK SKEW MINIMIZATION; DIFFERENTIAL SIGNALS; MULTIPLE LEVEL NETWORKS;

CAPACITANCE; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); OPTIMIZATION; REGRESSION ANALYSIS; TRANSISTORS;

LOGIC DESIGN;

EID: 2442489992     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

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