A reconfigurable unit for a clustered programmable-reconfigurable processor

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn 12, Issue , 2004, Pages 200-209

  Kujoth, Richard B ^a   Wang, Chi Wei ^a   Gottlieb, Derek B ^a   Cook, Jeffrey J ^a   Carter, Nicholas P ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

FPGA; Reconfigurable processor; Technology scaling

Indexed keywords

BANDWIDTH; COMPUTER PROGRAMMING; COMPUTER SCIENCE; DATA STORAGE EQUIPMENT; FIELD PROGRAMMABLE GATE ARRAYS; FILE ORGANIZATION; MULTIPROCESSING SYSTEMS;

CHIP MULTIPROCESSORS (CMP); RECONFIGURABLE PROCESSORS; TECHNOLOGY SCALING;

PROGRAM PROCESSORS;

EID: 2442480634     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/968280.968309     Document Type: Conference Paper

References (18)

1. NCSU Cadence Design Kit. http://www.cadence.ncsu.edu/.
2. S. Borkar. Design Challenges of Technology Scaling. Proceedings of the International Symposium on Microarchitecture, 19(4):23-29, July 1999.
3. P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, and I. Rahardja. The Design of a SRAM-Based Field-Programmable Gate Array-Part II: Circuit Design and Layout. IEEE Transactions on VLSI Systems, 7(3):321-330, Sept. 1999.
4. D. Cronquist, P. Franklin, C. Fisher, M. Figueroa, and C. Ebeling. Architecture Design of Reconfigurable Pipelined Datapaths. In Proceedings of the Twentieth Anniversary Conference on Advanced Research in VLSI, pages 23-40, 1999.
5. S. C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. R. Taylor, and R. Laufer. PipeRench: A Coprocessor for Streaming Multimedia Acceleration. In Proceedings of the International Symposium on Computer Architecture, pages 28-38, 1999.
6. D. B. Gottlieb, J. J. Cook, J. D. Walstrom, S. Ferrera, C.-W. Wang, and N. P. Carter. Clustered Programmable-Reconfigurable Processors. In Proceedings of the IEEE International Conference on Field-Programmable Technology, pages 134-141. IEEE, Dec. 2002.
7. S. Gupta, S. W. Keckler, and D. Burger. Technology Independent Area and Delay Estimates for Microprocessor Building Blocks. Technical Report 2000-05, Department of Computer Sciences, The University of Texas at Austin, 2000.
8. S. Hauck, M. M. Hosler, and T. W. Fry. High-Performance Carry Chains for FPGA's. IEEE Transactions on VLSI Systems, 8(2):138-147, Apr. 2000.
9. J. R. Hauser and J. Wawrzynek. Garp: A MIPS Processor with a Reconfigurable Coprocessor. In K. L. Pocek and J. Arnold, editors, IEEE Symposium on FPGAs for Custom Computing Machines, pages 12-21, Los Alamitos, CA, 1997. IEEE Computer Society Press.
10. R. Ho, K. W. Mai, and M. A. Horowitz. The Future of Wires. Proceedings of the IEEE, 89(4):490-504, Apr. 2001.
11. M. Hrishikesh, N. P. Jouppi, K. I. Farkas, D. Burger, S. W. Keckler, and P. Shivakumar. The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Delays. In Proceedings of the 29th Annual International Symposium on Computer Architecture, pages 14-24. IEEE, May 2002.
12. The International Technology Roadmap for Semiconductors 2001. Semiconductor Industry Association, 2001.
13. The International Technology Roadmap for Semiconductors 8002 Update. Semiconductor Industry Association, 2002.
14. J. Rose, R. J. Francis, D. Lewis, and P. Chow. Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency. IEEE Journal of Solid-State Circuits, 25(5):1217-1225, Oct. 1990.
15. I. Sutherland, B. Sproull, and D. Harris. Logical Effort: Designing Fast Cmos Circuits. Morgan Kaufmann Publishers, San Francisco, CA, 1999.
16. J. D. Walstrom. The Design of the Amalgam Reconfigurable Cluster. Master's thesis, University of Illinois at Urbana-Champaign, 2002.
17. S.-C. Wong, G.-Y. Lee, and D.-J. Ma. Modeling of Interconnect Capacitance, Delay, and Crosstalk in VLSI. IEEE Transactions on Semiconductor Manufacturing, 13(1):108-111, February 2000.
18. Z. A. Ye, A. Moshovos, S. Hauck, and P. Banerjee. CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Functional Unit. In Proceedings of the International Symposium on Computer Architecture, pages 225-235, 2000.