A high performance 32-bit ALU for programmable logic

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn 12, Issue , 2004, Pages 61-70

  Metzgen, Paul ^a  

^a Altera European Technology Centre   (United Kingdom)

Author keywords

ALU; Apex 20KE; FPGA; Nios; Programmable Logic; Soft processors

Indexed keywords

COMPUTER ARCHITECTURE; DECODING; FIELD PROGRAMMABLE GATE ARRAYS; FLIP FLOP CIRCUITS; INFORMATION RETRIEVAL; MULTI AGENT SYSTEMS; PROGRAM PROCESSORS; USER INTERFACES;

ALU; APEX 20KE; NIOS; PROGRAMMABLE LOGIC; SOFT PROCESSORS;

LOGIC PROGRAMMING;

EID: 2442441006     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/968280.968291     Document Type: Conference Paper

References (5)

1. Altera Corporation. Nios Programmer's Reference Manual. March 2001.
2. Altera Corporation. Apex 20K Programmable Logic Device Family Datasheet. November 1999.
3. Hennessy, J.L, Patterson, D.A., Goldberg, D. Computer Architecture: A Quantitative Approach, 3rd Edition. Kaufmann, May 2002. ISBN: 1558605967
4. Patterson, D.A., Hennessy, J.L., Indurkhya, N. Computer Organization and Design: The Hardware/Software Interface, 2nd Edition. Kaufmann, Aug 1997. ISBN: 1558604286
5. Fairchild Semiconductor. 74F181: 4-Bit Arithmetic Logic Unit. Datasheet, April 1988 Revised September 2000.