A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup

IEEE International Conference on Communications

Volumn 2, Issue , 2005, Pages 1048-1052

  Hanzawa, Satoru ^a   Sakata, Takeshi ^a   Kajigaya, Kazuhiko ^b   Takemura, Riichiro ^a   Sekiguchi, Tomonori ^a   Kawahara, Takayuki ^a  

^a HITACHI LTD   (Japan)

^b Elpida Memory Inc   (Japan)

Author keywords

CAM; Content addressable memory; Flow table lookup

Indexed keywords

BLOCK CODES; COMPUTER ARCHITECTURE; DATA COMPRESSION; DATA FLOW ANALYSIS; DATA REDUCTION; DYNAMIC RANDOM ACCESS STORAGE; NETWORK PROTOCOLS; TABLE LOOKUP;

CONTENT-ADDRESSABLE MEMORY (CAM); FLOW-TABLE LOOKUP; NETWORK PROCESSOR UNIT (NPU); QUATERNARY DATA;

DATA STORAGE EQUIPMENT;

EID: 24344462674     PISSN: 05361486     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. M. Ruiz-Sa'nchez, et al., "Survey and Taxonomy of IP Address Lookup Algorithms," in IEEE Network, March/April 2001, pp. 8-23.
2. Pankaj Gupta and Nick McKeown, "Algorithms for Packet Classification," in IEEE Network, March/April 2001, pp. 24-32.
3. S. Hanzawa et al., "A Dynamic CAM based on a One-Hot-Spot Block Code for Millions-Entry Lookup," in Symp. on VLSI Circuits Dig. Tech. Papers, 2004, pp. 382-385.
4. 75K72100 NSE Datasheet Brief. Available: http://www.idt.com/docs/ 75K76102_DS_97854.pdf
5. "How to input commands and estimate the capacity to manage packets in Ayama10K" (in Japanese). Available: http://www.cypress-japan.co.jp/ japanese/pdf/NSE10K_command.pdf