Comparative analysis of SMP click scheduling techniques

Lecture Notes in Computer Science

Volumn 3375, Issue , 2005, Pages 379-389

  Calarco, Giorgio ^a   Raffaelli, Carla ^a   Schembra, Giovanni ^b   Tusa, Giovanni ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SOFTWARE; INTERCONNECTION NETWORKS; NETWORK PROTOCOLS; ROUTERS; TELECOMMUNICATION INDUSTRY;

CLICK SCHEDULING; CPU; HARDWARE ROUTERS; MULTIPROCESSOR ARCHITECTURES;

SCHEDULING;

EID: 24144495263     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/978-3-540-30573-6_29     Document Type: Conference Paper

References (7)

1. The Click Modular Router Project: http://www.pdos.lcs.mit.edu/click/
2. Tilman Wolf: Design and Performance of Scalable High-Performance Programmable Routers, Dissertation Thesis, Washington University Sever Institute of Technology, Department of Computer Science, August 2002
3. Eddie Kohler: The Click modular router, PhD Thesis, MIT, 2000, available at http://www.pdos.lcs.mit.edu/papers/click:kohler-phd/thesis.pdf
4. E. Kohler, R. Morris, B. Chen, J. Jannotti, M.F. Kaashoek: The Click modular router. ACM Trans. Computer Systems 18, August 2000
5. B. Chen, R. Morris: Flexible Control of Parallelism in a Multiprocessor PC Router. Proceedings of the 2001 USENIX Annual Technical Conference (USENIX '01), June 2001, Boston, Massachusetts
6. J. Archibald, J.L. Baer: Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model. ACM Trans. Computer Systems Vol. 4, No. 4, November 1986
7. M. S. Papamarcos, J. H. Patel: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. The 11th Intl. Symposium on Computer Architecture, pp. 348-354, June 1984