A performance prediction of clock generation PLLs: A ring oscillator based PLL and an LC oscillator based PLL

IEICE Transactions on Electronics

Volumn E88-C, Issue 3, 2005, Pages 437-443

  Miyazaki, Takahito ^a   Hashimoto, Masanori ^a   Onodera, Hidetoshi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

Chip area; Clock generation PLL; Jitter; LC oscillator; Performance prediction; Power consumption; Ring oscillator

Indexed keywords

ENERGY UTILIZATION; JITTER; PARAMETER ESTIMATION; PROCESS CONTROL; SPURIOUS SIGNAL NOISE; TECHNOLOGY; VARIABLE FREQUENCY OSCILLATORS;

CHIP AREA; CLOCK GENERATION PLL; LC OSCILLATOR; PERFORMANCE PREDICTION; RING OSCILLATOR;

PHASE LOCKED LOOPS;

EID: 24144459883     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: 10.1093/ietele/e88-c.3.437     Document Type: Article

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