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note
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An acyclic circuit is a partially ordered set of gates. However, associating the circuit with constraints on the timing of the adversarial attack is a delicate issue. Suppose the circuit contains conditional gates controlled by random public classical registers. The gates on the target may or may not be applied depending on the values of the control registers. When the gates are not applied, the associated time-constraints of the adversarial attack disappear. In the extension to the usual acyclic circuit model, we consider all possible values of the control registers and the resulting sets of nontrivial partially ordered operations, and the corresponding constraints on the adversarial attack.
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