Benchmark results for high-speed 4-bit accumulators implemented in indium phosphide DHBT technology

International Journal of High Speed Electronics and Systems

Volumn 14, Issue 3, 2004, Pages 646-651

  Turner, Steven Eugene ^a   Kotecki, David E ^a  

^a University of Maine   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER SIMULATION; ELECTRIC POTENTIAL; SEMICONDUCTING INDIUM PHOSPHIDE; TRANSISTORS;

CLOCK FREQUENCY; HIGH SPEED ACCUMULATORS; LARGE SCALE CIRCUITS; POWER CONSUMPTION; POWER REDUCTION;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 24144433001     PISSN: 01291564     EISSN: None     Source Type: Journal    
DOI: 10.1142/S0129156404002612     Document Type: Conference Paper

References (5)

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2. C. G. Eckroot and S. I. Long, "A GaAs 4-bit adder-accumulator circuit for direct digital synthesis," IEEE JSSC 23 (1988) pp. 573-580
3. T. Mathew, S. Jaganathan, D. Scott, S. Krishnan, Y. Wei, M. Urtega, M. Rodwell, and S. Long, "2-bit adder carry and sum logic circuits clocking at 19 GHz clock frequency in transferred substrate HBT technology," in Proc. of IEEE International Conference on Indium Phosphide and Related Materials, Nara, Japan, May 2001, pp. 505-508.
4. T. Mathew, S. Jaganathan, D. Scott, S. Krishnan, Y. Wei, M. Urtega, M. J. W. Rodwell, and S. Long, "2-bit adder: carry and sum logic circuits at 19 GHz clock frequency in InAlAs/InGaAs HBT technology," Electronics Letters 37 (2001) pp. 1156-1157.
5. S. E. Turner, D. S. Jansen, and D. E. Kotecki, "4-bit adder-accumulator at 41 GHz clock frequency in InP DHBT technology," IEEE Microwave and Wireless Components Letters (2004), submitted for publication.