MINCE: A static global variable-ordering heuristic for SAT search and BDD manipulation

Journal of Universal Computer Science

Volumn 10, Issue 12, 2004, Pages 1562-1596

  Aloul, Fadi A ^a   Markov, Igor L ^b   Sakallah, Karem A ^b  

^a AMERICAN UNIVERSITY OF SHARJAH   (United Arab Emirates)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Backtrack search; BDDs; CNF; Decision heuristics; Formal verification; Partitioning; SAT; Variable ordering

Indexed keywords

EID: 23844509123     PISSN: 0958695X     EISSN: 09486968     Source Type: Journal    
DOI: None     Document Type: Article

References (62)

1. [Aloul et al., 2001] F. A. Aloul, I. L. Markov, and K. Sakallah, "Faster SAT and Smaller BDDs via Common Function Structure," in Proceedings of the International Conference on Computer Aided Design (ICCAD), pp. 443-448, 2001.
2. [Aloul et al., 2002a] F. A. Aloul, A. Ramani, I. L. Markov, and K. Sakallah, "Generic ILP versus Specialized 0-1 ILP: an Update," in Proceedings of the International Conference, on Computer Aided Design (ICCAD), pp. 450-457, 2002.
3. [Aloul et al., 2002b] F. A. Aloul, A. Ramani, I. L. Markov, and K. Sakallah, "Solving Difficult SAT Instances in the Presence of Symmetry," in Proceedings of the Design Automation Conference (DAC), pp. 731-736, 2002.
4. [Amir and McIlraith, 2000] E. Amir and S. McIlraith, "Improving the Efficiency of Reasoning Through Structure-Based Reformulation," in Proceedings of the International Symposium on Abstractions, Reformulation, and Approximation (SARA), Lecture Notes in Artificial Intelligence, vol. 1864, pp. 247-259, Springer 2000.
5. [Berman, 1991] C. Berman, "Circuit Width, Register Allocation, and Ordered Binary Decision Diagrams," in IEEE Transactions on Computer Aided Design, 10(8), pp. 1059-1066, 1991.
6. [Biere et al., 1999] A. Biere, A. Cimatti, E. M. Clarke, M. Fujita, and Y. Zhu, "Symbolic Model Checking Using SAT Procedures Instead of BDDs," in Proceedings of the Design Automation Conference (DAC), pp. 317-320, 1999.
7. [Brglez ef al., 1989] F. Brglez, D. Bryan, and K. Kozminski, "Combinational Problems of Sequential Benchmark Circuits," in Proceedings of the International Symposium on Circuits and Systems (ISCAS), pp. 1929-1934, 1989.
8. [Brglez and Fujiwara, 1985] F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN," in Proceedings of the International Symposium on Circuits and Systems (ISCAS), pp. 785-794, 1985.
9. [Breuer, 1977] M. Breuer, "Min-cut Placement," J. Design Automation Fault-Tolerant Computing, 1(4), pp. 343-362, 1977.
10. [Bryant, 1986] R. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," in IEEE Transactions on Computers, 35(8), pp. 677-691, 1986.
11. [Bryant, 1992] R. Bryant, "Symbolic Boolean Manipulation with Ordered Binary-Decision Diagrams," in ACM Computing Surveys, 24(3), pp. 293-318, September 1992.
12. [Bryant and Meinel, 2001] R. Bryant and C. Meinel, "Ordered Binary Decision Diagrams," in Logic Synthesis and Verification, S. Hassoun, and T. Sasao, eds., Kluwer Academic Publishers, Boston/Dordrecht/London, 2001.
13. [Caldwell et al., 2000a] A. Caldwell, A. Kahng, and I. L. Markov, "Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning," ACM Journal on Experimental Algorithms, vol. 5, 2000. http://www.jea.acm.org/volume5.html
14. [Caldwell et al., 2000b] A. Caldwell, A. Kahng, and I. L. Markov, "Can Recursive Bisection Produce Routable Placements'?" in Proceedings of the Design Automation Conference (DAC), pp. 477-482, 2000.
15. [Caldwell et al., 2000c] A. Caldwell, A. Kahng, and I. L. Markov, "Improved Algorithms for Hypergraph Bipartitioning," in Proceedings of the IEEE ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 661-666, 2000.
16. [Davis et al., 1962] M. Davis, G Logemann, and D. Loveland, "A Machine Program for Theorem-Proving," in Communications of the Association for Computing Machinery, vol. 5, pp. 394-397, 1962.
17. [Drechsler and Becker, 1998] R. Drechsler and B. Becker, "Binary Decision Diagrams, Theory and Implementation," Kluwer Academic Publishers, 1998.
18. [DIMACS] DIMACS Challenge benchmarks in ftp://Dimacs.rutgers.EDU/pub/ challenge/sat/benchmarks/cnf.
19. [Dunlop and Kernighan, 1985] A. Dunlop and B. Kernighan, "A Procedure for Placement of Standard-Cell VLSI Circuits," in IEEE Transactions on Computer-Aided Design, 1(4), pp. 92-98, 1985.
20. [Fiduccia and Mattheyses, 1982] C. Fiduccia and R. Mattheyses, "A Linear-Time Heuristic for Improved Network Partitions," in Proceedings of the Design Automation Conference (DAC), pp. 241-247, 1982.
21. [Fujii et al., 1993] H. Fujii, G. Ootomo, and C. Hori, "Interleaving Based Variable Ordering Methods for Ordered Binary Decision Diagrams," in Proceedings of the International Conference on Computer Aided Design (ICCAD), pp. 38-41, 1993.
22. [Fujita et al., 1988] M. Fujita, H. Fujisawa, and N. Kawato, "Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams," in Proceedings of the International Conference on Computer Aided Design (ICCAD), pp. 2-5, 1988.
23. [Garey and Johnson, 1979] M. Garey and D. Johnson, "Computers and Intractability: A Guide to the Theory of NP-Completeness," W. H. Freeman & Co., 1979.
24. [Goldberg and Novikov, 2002] E. Goldberg and Y. Novikov, "BerkMin: A Fast and Robust SAT-Solver," in Proceedings of the Design Automation and Test in Europe Conference (DATE), pp. 142-149, 2002.
25. [Gomes et al., 1998] C. Gomes, B. Selman, and H. Kautz, "Boosting Combinatorial Search Through Randomization," in Proceedings of the National Conference on Artificial Intelligence (AAAI), pp. 431-437, 1998.
26. [Hachtel and Somenzi, 2000] G. Hachtel and F. Somenzi, "Logic Synthesis and Verification Algorithms," Kluwer, 3rd ed., 2000.
27. [Huang and Darwiche, 2003] J. Huang and A. Darwiche, "A Structure-Based Ordering Heuristic for SAT," in Proceedings of the International Joint Conference on Artificial Intelligence (IJCAI), 2003.
28. [ISCAS, 1985] ISCAS'85 Benchmark Information, http://www.cbl.ncsu.edu/ www/CBL_Docs/iscas85.html
29. [Janssen, 2001] G. Janssen, "Design of a Pointerless BDD Package," in International Workshop on Logic Synthesis (IWLS), 2001.
30. [Jin et al., 2002] H. Jin, A. Kuehlman, and F. Somenzi, "Fine-grain Conjunction Scheduling for Symbolic Reachability Analysis", in Tools and Algorithms for Construction and Analysis of Systems (TACAS), pp. 312-326, 2002.
31. [Karypis et al., 1997] G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multilevel Hypergraph Partitioning: Applications in VLSI Design," in Proceedings of the Design Automation Conference (DAC), pp. 526-529, 1997.
32. [Kernighan and Lin, 1970] B. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs," Bell System Technical Journal, 49(1), pp. 291-307, 1970.
33. [Larrabee, 1992] T. Larrabee, "Test Pattern Generation Using Boolean Satisfiability," IEEE Transactions on Computer-Aided Design, 11(1), pp. 4-15, 1992.
34. [Lu et al., 2000] Y. Lu, J. Jain, and K. Takayama, "BDD Variable Ordering Using Window-based Sampling," in International Workshop on Logic Synthesis (IWLS), 2000.
35. [Malik et al., 1988] S. Malik, A. Wang, R. Brayton, and A. Sangiovanni-Vincentelli, "Logic Verification Using Binary Decision Diagrams in a Logic Synthesis Environment," in Proceedings of the International Conference on Computer Aided Design (ICCAD), pp. 6-9, 1988.
36. [Minato et al., 1990] S. Minato, N. Ishiura, and S. Yajima, "Shared Binary Decision Diagrams with Attributed Edges for Efficient Boolean Function Manipulation," in Proceedings of the Design Automation Conference (DAC), pp. 52-57, 1990.
37. [Moskewicz et al., 2001] M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an Efficient SAT Solver," in Proc. of the Design Automation Conference (DAC), pp. 530-535, 2001.
38. [Nam et al., 2001] G. Nam, F. A. Aloul, K. Sakallah, and R. Rutenbar, "A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints," in Proceedings of the International Symposium on Physical Design (ISPD), pp. 222-227, 2001.
39. [Panda and Somenzi, 1995] S. Panda and F. Somenzi, "Who Are the Variables in Your Neighborhood," in Proceedings of the International Conference on Computer Aided Design (ICCAD), pp. 74-77, 1995.
40. [Prasad et al., 1999] M. Prasad, P. Chong, and K. Keutzer, "Why is ATPG Easy?" in Proceedings of the Design Automation Conference (DAC), pp. 22-28, 1999.
41. [Rudell, 1993] R. Rudell, "Dynamic Variable Ordering for Ordered Binary Decision Diagrams," in Proceedings of the International Conference on Computer Aided Design (ICCAD), pp. 42-47, 1993.
42. [Ryan] L. Ryan, "Siege SAT Solver", http://www.cs.sfu.ca/ ~loryan/personal/
43. [SAT 2004] SAT 2004 Competition, http://www.satlive.org/SATCompetition
44. [SATLIB] Satlib SAT Benchmarks, http://www.satlib.org
45. [Shacham and Zarpas, 2003] O. Shacham and E. Zarpas, "Tuning the VSIDS Decision Heuristic for Bounded Model Checking," in Microprocessor Test and Verification (MTV), pp. 75-82, May 2003.
46. [Silva and Sakallah, 1996] J. Silva and K. Sakallah, "GRASP-A New Search Algorithm for Satisfiability," in Proceedings of the International Conference on Computer Aided Design (IC-CAD), pp. 220-227, 1996.
47. [Silva and Sakallah, 1997] J. Silva and K. Sakallah, "Robust Search Algorithms for Test Pattern Generation," in Proceedings of the IEEE Fault-Tolerant Computing Symposium, pp. 152-161, 1997.
48. [Silva et al., 1998] L. Silva, J. Silva, L. Silveira, and K. Sakallah, "Timing Analysis Using Prepositional Satisfiability," in IEEE International Conference on Electronics, Circuits and Systems, 1998.
49. [Somenzi, 1997] F. Somenzi, "Colorado University Decision Diagram package," 1997. http://vlsi.colorado.edu/~fabio/CUDD
50. [Somenzi, 2001] F. Somenzi, "Efficient Manipulation of Decision Diagrams," in International Journal on Software Tools for Technology Transfer (STTT), 3(2), pp. 171-181, 2001.
51. [Stålmarck, 1994] G Stålmarck, "System for Determining Propositional Logic Theorems by Applying Values and Rules to Triplets that are Generated from Boolean Formula," United States Patent no. 5,276,897, 1994.
52. [Stephan et al., 1996] P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli, "Combinational Test Generation Using Satisfiability," in IEEE Transactions on Computer-Aided Design, 15(9), pp. 1167-1175, 1996.
53. [Tseitin, 1983] G. Tseitin, "On the Complexity of Derivation in Propositional Calculus," in Studies in Constructive Mathematics and Mathematical Logic, Part 2, pp. 115-125, 1968.
54. Reprinted in J. Siekmann, and G. Wrightson, eds., Automation of Reasoning, Vol. 2, Springer-Verlag, pp. 466-483, 1983.
55. [Urquhart, 1987] A. Urquhart, "Hard Examples for Resolution," in Journal of the ACM, 34(1), pp. 209-219, 1987.
56. [Vazirani, 2001] V. Vazirani, "Appoximation Algorithms", Springer, pp. 378, 2001.
57. [Velev and Bryant, 1999] M. Velev and R. Bryant, "Superscalar Processor Verification Using Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic," in Proceedings of the Conference on Correct Hardware Design and Verification Methods (CHARME), LNCS 1703, pp. 37-53, 1999.
58. [Wang and Clarke, 2001] D. Wang and E. Clarke, "Efficient Formal Verification through Cutwidth," in IEEE International High Level Design Validation and Test Workshop (HLDVT), 2001.
59. [Wang, 1997] J. Wang. "Branching Rules for Propositional Satisfiability Test." in DIMACS series in Discrete Mathematics and Theoretical Computer Science, vol. 35, 1997.
60. [Wood and Rutenbar, 1998] R. Wood and R. Rutenbar, "FPGA Routing and Routability Estimation Via Boolean Satisfiability," in IEEE Transactions on VLSI, 6(2), pp. 222-231, 1998.
61. [Yang and Ciesielski, 2002] C. Yang and M. Ciesielski, "BDS: A BDD-Based Logic Optimization System," in IEEE Transactions on Computer-Aided Design, 21(7), pp. 866-876, 2002.
62. [Zhang, 1997] H. Zhang, "SATO: An Efficient Propositional Prover," in International Conference on Automated Deduction, pp. 272-275, 1997.