Space processor radiation mitigation and validation techniques for an 1, 800 MIPS processor board

European Space Agency, (Special Publication) ESA SP

Volumn , Issue 536, 2004, Pages 347-352

  Hillman, R ^a   Swift, G ^b   Layton, P ^a   Conrad, M ^a   Thibodeau, C ^a   Irom, F ^b  

^a MAXWELL TECHNOLOGIES   (United States)

^b CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MICROPROCESSOR INDUSTRY; PROCESSOR BOARDS; RADIATION TESTING; SPACE PROCESSOR RADIATION;

COMPUTER ARCHITECTURE; INFORMATION TECHNOLOGY; MICROPROCESSOR CHIPS; PERSONAL COMPUTERS; RADIATION EFFECTS; SILICON ON INSULATOR TECHNOLOGY; STORAGE ALLOCATION (COMPUTER);

PROGRAM PROCESSORS;

EID: 23844477594     PISSN: 03796566     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. F. Irom, F. Farmanesh, A. Johnston, G. Swift and D. Millward, " Single-Event Upset in Commercial Silicon-On-Insulator PowerPC Microprocessors", IEEE Trans. Nucl. Sci., vol. 49, No. 6, Dec 2002, pp3148-3155.
2. G. Swift, F. Farmanesh, S. Guertin, F. Irom and D. Millward. "SingleEvent upset in the PowerPC750 Microprocessor", IEEE Trans. Nucl. Sci., vol. 48, NO. 6, Dec 2001, pp1822-1827.
3. N. Haddad, R. Brown, T. Cronauer, H. Phan, "Radiation Hardened COTS-based 32-bit Microprocessor", RADECS proceedings 1999, pp 593-597.