A parallel architectural implementation of the new three-step search algorithm for block motion estimation

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 1071-1076

  Seth, Kavish ^a   Rangarajan, P ^b   Srinivasan, S ^c   Kamakoti, V ^c   Kuteshwar, V Bala ^a  

^a Atheros India LLC   (India)

^b SVEC ^*  (United States)

^c INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

Author keywords

[No Author keywords available]

Indexed keywords

FULL SEARCH (FS); NEW THREE STEP SEARCH (NTSS); QUASI-STATIONARY BLOCKS; THREE STEP SEARCH (TSS);

ALGORITHMS; BANDWIDTH; BIT ERROR RATE; COMPUTATIONAL COMPLEXITY; ERROR ANALYSIS; HIERARCHICAL SYSTEMS; HIGH DEFINITION TELEVISION; IMAGE CODING; REAL TIME SYSTEMS; SWITCHING; VECTORS;

MOTION ESTIMATION;

EID: 2342644046     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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