Leakage-proof domino circuit design for deep sub-100nm technologies

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 222-227

  Yang, Ge ^a   Wang, Zhongda ^a   Kang, Sung Mo ^a  

^a University of California Santa Cruz   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGN; DOMINO CIRCUITS;

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; GATES (TRANSISTOR); LEAKAGE CURRENTS; MOS DEVICES; POWER ELECTRONICS; SILICA;

ELECTRIC NETWORK ANALYSIS;

EID: 2342612805     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. S. Shigematsu, S. Mutoh, Y. Matsuya, and J. Yamada, "A 1-V high-speed MTCMOS circuit scheme for power-down applications", Symposium on VLSI Circuits, Digest of Technical Papers, 1995, Page(s): 125-126
2. J. T. Kao and A. P. Chandrakasan, "Dual-threshold voltage techniques for low-power digital circuits", IEEE Journal of Solid-State Circuits, Volume: 35 Issue: 7, July 2000, Page(s): 1009-1018
3. 2001 International Technology Roadmap for Semiconductors, http://public.itrs.net/
4. H. Sasaki, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, and H. Iwai, "1.5 nm direct-tunneling gate oxide Si MOSFET's", IEEE Transactions on Electron Devices, Volume:43, Issue:8, Aug. 1996, Page(s): 1233-1242
5. T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors", VLSI Technology, Digest of Technical Papers, 2000, Page(s): 174-175
6. Chang-Hoon Choi, Kwang-Hoon Oh, Jung-Suk Goo, Zhiping Yu, and R. W. Dutton, "Direct tunneling current model for circuit simulation", International Electron Devices Meeting, IEDM Technical Digest, 1999, Page(s): 735-738
7. K. M. Cao, W.-C. Lee, W. Liu, X. Jin, P. Su, S. K. H. Fung, J. X. An, B. Yu, and C. Hu, "BSIM4 gate leakage model including source-drain partition", International Electron Devices Meeting, IEDM Technical Digest, 2000, Page(s): 815-818
8. T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai," Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free Giga-scale integration", Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000, Page(s): 409-412
9. F. Hamzaoglu and M. R. Stan, "Circuit-level techniques to control gate leakage for sub-100nm CMOS", Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Page(s): 60-63
10. Yee Chia Yeo, Qiang Lu, Wen Chin Lee, Tsu-Jae King, Chenming Hu, Xiewen Wang, Xin Guo, and T. P. Ma, "Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric", IEEE Electron Device Letters, Volume: 21, Issue: 11, Nov. 2000, Page(s): 540-542
11. A. Alvandpour, R. K. Krishnamurthy, K. Soumyanath, and S. Y. Borkar, "A sub-130-nm conditional keeper technique", IEEE Journal of Solid-State Circuits, Volume: 37 Issue: 5, May 2002, Page(s): 633-638
12. Berkeley Predictive Technology Model (BPTM), http://www-device.eecs. berkeley.edu/~ptm/download.html
13. True-Hspice®Device Models Reference Manual, Release 2002.2
14. M. H. Anis, M. W. Allam, and M. I. Elmasry, "Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 10 Issue: 2, Apr 2002, Page(s): 71-78
15. S. Knowles, "A family of adders", 15th IEEE Symposium on Computer Arithmetic, Proceedings, 2001, Page(s): 277-281
16. G. Yang, S. O. Jung, S. H. Kim and S. M. Kang, "A Low-Power 2.1 GHz 32-bit Carry Lookahead Adder Using Dual Path All-N-Logic", 45th IEEE International Midwest Symposium on Circuits and Systems, Volume: 2, 2002, Page(s): 298-301
17. P. M. Kogge and H. S. Stone, "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations," IEEE Trans., Aug. 1973, C-22(8):786-793.
18. J. Tschanz, et al., "Dynamic-Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors", IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2003, Page(s): 102-103