An ILP formulation for system level throughput and power optimization in multiprocessor SoC architectures

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 255-260

  Srinivasan, Krishnan ^a   Chatha, Karam S ^a  

^a Arizona State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC POWER MANAGEMENT (DPM); DYNAMIC VOLTAGE SCALING (DVS); INTEGER LINEAR PROGRAMMING (ILP); SYSTEM-ON-CHIP (SOC);

COMPUTER ARCHITECTURE; CONSTRAINT THEORY; ELECTRIC POTENTIAL; EMBEDDED SYSTEMS; ENERGY UTILIZATION; INTEGER PROGRAMMING; LINEAR PROGRAMMING; MATHEMATICAL TRANSFORMATIONS; OPTIMIZATION; SET THEORY; SYSTEMS ANALYSIS;

MULTIPROCESSING SYSTEMS;

EID: 2342565011     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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