Evaluation of interconnect technologies for power semiconductor devices

InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITHERM

Volumn 2002-January, Issue , 2002, Pages 1089-1096

  Calata, J N ^a   Lu, Guo Quan ^a   Luechinger, C ^b  

^a State University   (United States)

^b Orthodyne Electronics   (United States)

Author keywords

Acoustic testing; Bonding; Electronics packaging; Fabrication; Integrated circuit packaging; Power semiconductor devices; Power system interconnection; Power system reliability; Semiconductor device packaging; Wire

Indexed keywords

BONDING; CHIP SCALE PACKAGES; COST BENEFIT ANALYSIS; ELECTRIC POWER SYSTEM INTERCONNECTION; ELECTRONICS PACKAGING; FABRICATION; FLIP CHIP DEVICES; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT TESTING; POWER ELECTRONICS; RELIABILITY; SEMICONDUCTOR DEVICE TESTING; SOLDERING; WIRE; WIRE PRODUCTS;

ACOUSTIC TESTING; INTEGRATED CIRCUIT PACKAGING; POWER SEMICONDUCTOR DEVICES; POWER SYSTEM INTERCONNECTION; POWER SYSTEM RELIABILITY; SEMICONDUCTOR DEVICE PACKAGING;

SEMICONDUCTOR DEVICES;

EID: 2342545350     PISSN: 19363958     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITHERM.2002.1012579     Document Type: Conference Paper

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